Silicon Labs /BGM220SC22WGA /RAC_S /SYTRIM1

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Interpret as SYTRIM1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RXLO)SYLODIVLDOTRIMCORE 0 (vreg_1p08)SYLODIVLDOTRIMNDIO 0 (load_8ua)SYMMDREPLICA1CURRADJ 0 (load_32u)SYMMDREPLICA2CURRADJ 0 (bias_14uA)SYTRIMMMDREGAMPBIAS 0 (C_000f)SYTRIMMMDREGAMPBW 0 (adc_clk_div8)SYLODIVRLOADCCLKSEL 0 (div2)SYLODIVSGTESTDIV

SYLODIVSGTESTDIV=div2, SYTRIMMMDREGAMPBIAS=bias_14uA, SYLODIVLDOTRIMNDIO=vreg_1p08, SYMMDREPLICA2CURRADJ=load_32u, SYLODIVLDOTRIMCORE=RXLO, SYLODIVRLOADCCLKSEL=adc_clk_div8, SYTRIMMMDREGAMPBW=C_000f, SYMMDREPLICA1CURRADJ=load_8ua

Fields

SYLODIVLDOTRIMCORE

SYLODIVLDOTRIMCORE

0 (RXLO): undefined

3 (TXLO): undefined

SYLODIVLDOTRIMNDIO

SYLODIVLDOTRIMNDIO

0 (vreg_1p08): undefined

1 (vreg_1p11): undefined

2 (vreg_1p15): undefined

3 (vreg_1p18): undefined

4 (vreg_1p21): undefined

5 (vreg_1p24): undefined

6 (vreg_1p27): undefined

7 (vreg_1p29): undefined

8 (vreg_1p32): undefined

9 (vreg_1p34): undefined

SYMMDREPLICA1CURRADJ

SYMMDREPLICA1CURRADJ

0 (load_8ua): undefined

1 (load_16u): undefined

2 (load_20ua): undefined

3 (load_28ua): undefined

4 (load_24ua): undefined

5 (load_32ua): undefined

6 (load_36ua): undefined

7 (load_44ua): undefined

SYMMDREPLICA2CURRADJ

SYMMDREPLICA2CURRADJ

0 (load_32u): undefined

1 (load_64u): undefined

2 (load_96u): undefined

3 (load_128u): undefined

4 (load_160u): undefined

5 (load_192u): undefined

6 (load_224u): undefined

7 (load_256u): undefined

SYTRIMMMDREGAMPBIAS

SYTRIMMMDREGAMPBIAS

0 (bias_14uA): undefined

1 (bias_20uA): undefined

2 (bias_26uA): undefined

3 (bias_32uA): undefined

4 (bias_38uA): undefined

5 (bias_44uA): undefined

6 (bias_50uA): undefined

7 (bias_56uA): undefined

SYTRIMMMDREGAMPBW

SYTRIMMMDREGAMPBW

0 (C_000f): undefined

1 (C_300f): undefined

2 (C_600f): undefined

3 (C_900f): undefined

SYLODIVRLOADCCLKSEL

SYLODIVRLOADCCLKSEL

0 (adc_clk_div8): undefined

1 (adc_clk_div16): undefined

SYLODIVSGTESTDIV

SYLODIVSGTESTDIV

0 (div2): undefined

1 (div3): undefined

2 (div4): undefined

3 (div6): undefined

4 (div8): undefined

5 (div12): undefined

6 (div16): undefined

7 (div12x): undefined

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